Job
- Level
- Senior
- Job Field
- Embedded
- Employment Type
- Full Time
- Contract Type
- Permanent employment
- Location
- Munich
- Working Model
- Onsite
Job Summary
In this role, you will design verification environments for interface IP protocols, execute detailed test plans, and mentor junior engineers in verification using System Verilog and UVM.
Job Technologies
Your role in the team
- Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
- Collaborating with design and architecture teams to identify and fix bugs.
- Performing all tasks related to verifying a complex digital IP including detailed test plans, functional coverage analysis and driving coverage closure.
- Mentoring and guiding junior verification engineers in best practices and methodologies.
- Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality.
- Documenting design specifications, test plans, and verification reports.
- Proficiency in System Verilog, UVM, SVA, and other verification techniques.
- Strong understanding of digital design and verification concepts.
- Excellent problem-solving skills and attention to detail.
This text has been machine translated. Show original
Our expectations of you
Qualifications
- Proficiency in digital design and verification methodologies.
- Expertise in using advanced verification techniques.
- Vertrautheit mit Skriptsprachen wie Python oder Perl zur Automatisierung.
- Detail-oriented with a strong analytical mindset.
- Excellent communicator, able to convey complex technical concepts clearly.
- Collaborative team player who thrives in a dynamic environment.
- Proactive and self-motivated, with a commitment to continuous learning.
- A results-driven professional committed to delivering high-quality work.
- Mentor and leader, capable of guiding and developing junior engineers.
Experience
- Experience with developing testbenches using SystemVerilog and UVM.
This text has been machine translated. Show original
What we offer
- You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions.
- The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges.
- You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.
This text has been machine translated. Show original
Topics that you deal with on the job
Job Locations
This is your employer
Synopsys
As a leading software manufacturer, Synopsys Inc. produces EDA software (electronic design automation) for the electronics industry.
Description
- Company Type
- Established Company
- Working Model
- Hybrid, Onsite
- Industry
- Internet, IT, Telecommunication
ASIC Digital Design Verification Principal Engineer
- Location
- Munich
- Working Model
- Onsite
- Diversity
- Open for all genders
- English Only
- English only required
